During the manufacture of semiconductor memories, such as a synchronous dynamic random access memories ("SDRAMs"), it is necessary to test each memory cell to ensure it is operating properly. Electronic and computer systems containing semiconductor memories also normally test the memories when power is initially applied to the system.
A conventional memory device is illustrated in FIG. 1. The memory device is an SDRAM 10 which includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory bank arrays 20 and 22 depending upon the state of a bank address bit forming part of the row address. The arrays 20 and 22 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 20 and 22 is a respective row address latch 26, which stores the row address, and a row decoder 28, which applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20 and 22. The row addresses are generated for refresh purposes by a refresh counter 30 that is controlled by a refresh controller 32.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. Depending on the operating mode of the SDRAM 10, the column address is either coupled through a burst counter 42 to a column address buffer 44, or to the burst counter 42, which applies a sequence of column addresses to the column address buffer 44 starting at the column address output by the address register 12. In either case, the column address buffer 44 applies a column address to a column decoder 48, which applies various column signals to respective sense amplifiers and associated column circuits 50 and 52 for the respective arrays 20 and 22.
Data to be read from one of the arrays 20 or 22 are coupled from the arrays 20 or 22, respectively, to a data bus 58 through the column circuit 50 or 52, respectively, and a read data path that includes a data output register 56. Data to be written to one of the arrays 20 or 22 are coupled from the data bus 58 through a write data path, including a data input register 60, to one of the column circuits 50 or 52 where they are transferred to one of the arrays 20 or 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuits 50 and 52 by, for example, selectively masking data to be read from the arrays 20 and 22.
The above-described operation of the SDRAM 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by the memory controller, are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the "*" designates the signal as active low. The command decoder 68 generates a sequence of control signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. The control signals include signals to activate rows of memory cells in the arrays 20, 22, signals to equilibrate digit lines in the arrays 20, 22, and signals to apply power to sense amplifiers in the column circuits 50, 52. These control signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
During testing of the SDRAM 10, each memory cell must be tested to ensure it is operating properly. In order to facilitate testing high capacity SDRAMs, test modes have been employed that allow reading and writing operations to be performed on multiple arrays simultaneously, thus reducing the time required to test every memory cell. Generically, a test mode allows the normal operation of the SDRAM to be suspended during the time the device is in the test mode. To test the memory cells, a memory tester applies address, data, and control signals to the SDRAM to place the device in test mode, and write data to and read data from all the memory cells in the arrays. In a typical prior art test method, data having a first binary value (e.g., a "1") is written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a "0") is typically written to and read from the memory cells. The memory tester determines a memory cell is defective when the data written to the memory cell does not equal the data read from the memory cell.
Although the test method described above may be effective in determining the gross functionality of the SDRAM, it would be ineffective in identifying other failure mechanisms. For example, if the row and column address decoders of the SDRAM were defective and could address only a limited number of the cells in the entire array, the SDRAM device would nevertheless pass the test pattern described above. However, if complementary data were written to each cell immediately after being read, instead of reading through the entire array before writing new data, the memory tester would have detected an error, and identify the SDRAM as a defective memory device. Such a test pattern is generally referred to as a "MARCH" test, and may be performed by incrementing or decrementing through the available memory cell addresses. Thus, as illustrated by the previous example, various other data test patterns, as well as different signal timing, may be applied by the memory tester during testing of the SDRAM to identify different failure mechanisms.
In addition to testing the functionality of the SDRAM, various test patterns and timing may also be used to measure various performance characteristics of the SDRAM. One example is measuring the maximum data retention time of the memory cells of the SDRAM. A "checkerboard" pattern may be written to the array so that physically adjacent memory cells have opposite data polarities. Such a pattern creates a condition where adjacent memory cells may influence leakage currents. After a predetermined delay time, the tester begins reading the array to check if the polarity of any of the cells has changed. The test is repeated with progressively longer delay times until the SDRAM fails. The corresponding delay time is taken to be an approximation of the device's maximum data retention time.
In spite of the various data patterns and signal timing that may be applied by the memory tester to the SDRAM during testing, there may be subtle failure mechanisms and performance characteristics that are difficult, if not impossible, to test or measure. These marginal failure mechanisms may be masked by the inherent operation of the SDRAM itself. That is, a sequence of internal operations that occur after a command is initiated by the SDRAM may be carried out in a manner that prevents a marginal failure from being detected. For example, marginal failures related to signal line coupling, or signal line shorting are some examples of the type of failure mechanisms that may be hidden during the normal operation of the SDRAM. As a consequence, an SDRAM may pass functional testing and burn-in testing, but the marginal failure mechanism may continue to degrade until the SDRAM fails in the field.
Therefore, there is a need for a method and apparatus that increases the flexibility of testing memory devices.